The present invention relates generally to integrated circuits, and in particular, to a method and system for measuring local electrical power consumption in an integrated circuit. The method may be used in electronic circuit design, as well as for performing self-tests in integrated circuit chips.
In the design and during operation of electronic systems, power consumption is an important parameter to be considered. On the one hand, “Green IT” calls for total energy consumption of electronic systems to be minimized. On the other hand, local power consumption within the electronic system is a crucial factor to take into account if overheating and thus malfunction of the system is to be avoided. In order to ensure reliable functionality, local power consumption within the system has to be assessed so that adequate cooling can be applied both locally and globally. This is especially true in high-end integrated circuits (ICs) where electronic components are closely packed and may consume considerable electrical power during operation. These types of electronics require cooling functionalities which need to be carefully designed, located and dimensioned according to the system's prospective local power consumption during typical activities.
Power consumption is an especially important parameter in high end VLSI (very large scale integration) chip designs, since all components have to be placed and spaced in such a way that they can be provided with adequate local cooling at any time during system operation. Failure analysis based on (local) power dissipation and/or local temperature is therefore becoming more and more important, e.g., for optimizing packaging density, energy efficiency, etc. In an effort to ensure that the IC under consideration will operate as desired, models of the (local) power dissipation within the IC are synthesized and used for modeling in order to determine whether the actual power distribution within the IC and its cooling is sufficient to meet certain design requirements. The validity of these models needs to be verified by taking real-world (i.e., physical) measurements of the actual power dissipation within the design. It is thus desirable to be able to accurately measure local power consumption in an electronic system comprising integrated circuits and to estimate prospective power consumption during the early stages of the system design, preferably during integrated circuit design.
The verification of power consumption associated with specific activities and load situations of the chip requires a measurement technique which yields reliable power data for individual VLSI (very large scale integration) chips/circuits as a whole or one or more parts of them. These data may then be used for verifying the anticipated system power and cooling requirements, as well as to model hardware to verify the individual power consumption for certain system load situations. The measurements have to be accurate and activity-related in the sense that they should furnish information on actual power demand of specific hardware activities in a system environment.
Various methods of measuring power consumption of an electronic system are known. For example, local power consumption within an IC chip may be estimated using on-chip thermal sensors. These sensors measure temperature within the chip and are thus capable of detecting regions of increased power consumption, so-called “hot spots”. However, the measurements of thermal sensors represent time and location averages of the actual power consumption of the chip and therefore only yield indirect feedback, and are not capable of furnishing activity-specific and time-resolved data.
Power consumption in a part of an electronic circuit can be measured directly by simultaneously measuring time domain voltage U and current I within this part of the electronic circuit and calculating P=U*I. In particular, average power consumption can be evaluated based on measurements of average voltage and average current during specific hardware operation in a steady state system environment. This quasi-static method, however, only yields a time average of power consumption and cannot furnish time resolved data necessary for verifying a modeled and simulated time domain power consumption spectrum.
If a time resolved measurement of the power consumption is required, current and voltage have to be determined with the appropriate temporal resolution. While time-resolved on-chip voltage measurements are state of the art during chip operation and yield reliable results, on-chip power supply current measurements—if they are possible at all—systematically impact the power supply path and are thus inherently error-prone. As an example, current measurement based on the Hall effect (i.e., measurement of magnetic field using a GMR sensor) will yield a spatial average on a scale which, in general, is much larger than the spatial extent of a specific chip region under consideration.
U.S. Pat. No. 7,138,815 describes an on-chip self test system capable of measuring voltage between on-chip test points during a current discontinuity. The current discontinuity may be generated by turning on a first configurable logic block and then, after a selected period, turning on a second configurable logic block to create a current waveform. The resulting voltage and current data may be used for evaluating the chip's impedance profile. A different method for determining impedance profiles at different locations in a chip is described in U.S. Pat. No. 6,768,952. In this method, the chip is activated by different codes that, when executed, produce constant current levels. Subsequently, the clock frequency is toggled, thus creating a periodic current waveform, and the resulting voltage is measured. The impedance profile is calculated from the Fourier transform of the measured voltage and the Fourier transform of the periodic current waveform.
While on-chip measurement methods for determining impedance profiles of an integrated circuit chip are available, these do not furnish data on the chip's local power consumption. Thus, there is a need for an accurate method for determining time resolved power consumption in conjunction with a specific activity executing in a specific region of an electronic circuit. This method should be applicable to model-to-hardware verification during electronic circuit design and therefore should yield quantitative results and provide guidance to specific improvements. This method should also be adaptable to be used as part of a self test mechanism within the electronic circuit and thus enable fast and inexpensive manufacturing tests as well as providing power sanity checks during operation.